View ILX115LA_253512.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ILX115LA
5000-pixel x 3 line CCD Linear Sensor (Color) For the availability of this product, please contact the sales office.
Description The ILX115LA is a reduction type CCD linear sensor developed for color DPPC. This sensor reads A3-size documents at a density of 400 DPI (Dot Per Inch). Features * Number of effective pixels: 15000 pixels (5000 pixels x 3) * Pixel size: 14m x 14m (14m pitch) * Distance between line: 84m (6 lines) * Maximum data rate: 30MHz/color (20MHz/color during clamp circuit usage) * Single 9V power supply * Input Clock Pulse: CMOS 5V drive * Number of output: 6 (2/color) * Package: 44pin SDIP (400mil) Absolute Maximum Ratings * Supply voltage VDD * Operating temperature * Storage temperature Pin Configuration (Top View)
29 16 10 4 VREF 2L 37 39 6 2 VOUT-ODD (B) 43 GND 44 VOUT-EVEN (B) 1 3 8 15 Output circuit-EVEN (G) VOUT-EVEN (G) VOUT-ODD (G) 1 CCD register (G) ROG (G) Sensor (G) ROG (G) CCD register (G)
44 pin SDIP (Cer-DIP)
Block Diagram
28 ROG (G) 18 ROG (R) 25 ROG (B)
11 -10 to +60 -30 to +80
V C C
26 VDD
21 GND
VOUT-EVEN (B) VOUT-ODD (R) VOUT-EVEN (R) VDD NC RS NC CLP NC 2 NC NC NC
1 2 3 4 5 6 7 8 9 10 R 11 12 13 B 1 1 1
44 GND 43 VOUT-ODD (B)
1 34
42 VOUT-EVEN (G) 41 VOUT-ODD (G) 40 NC 39 VREF 37 2L 36 NC 35 NC 34 1
CCD register (R) ROG (R) Sensor (R) ROG (R) CCD register (R)
CCD register (B) ROG (B) Sensor (B) ROG (B) CCD register (B)
33 NC 32 NC 31 NC 30 NC 29 1
NC 14 SWCLP 2 NC ROG (R) NC NC GND NC 15 16 17 18 19 5000 5000
27 NC 26 VDD 5000 25 ROG (B) 24 NC 23 NC
20 21 22
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
42
28 ROG (G)
E99705-PS
VOUT-ODD (R) VOUT-EVEN (R) CLP SWCLP
41
Output circuit-EVEN (R)
Output circuit-EVEN (B)

Output circuit-ODD (G) Output circuit-ODD (R) Output circuit-ODD (B)
G
RS
38 NC
VDD 2
2
ILX115LA
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Symbol VOUT-EVEN (B) VOUT-ODD (R) VOUT-EVEN (R) VDD NC RS NC CLP NC 2 NC NC NC NC SWCLP 2 NC ROG (R) NC NC GND NC Description Signal output (B) Signal output (R) Signal output (R) 9V power supply NC Clock pulse input NC Clock pulse input NC Clock pulse input NC NC NC NC Clamp switch Clock pulse input NC Clock pulse input NC NC GND NC Pin No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol NC NC ROG (B) VDD NC ROG (G) 1 NC NC NC NC 1 NC NC 2L NC VREF NC VOUT-ODD (G) NC NC Clock pulse input 9V power supply NC Clock pulse input Clock pulse input NC NC NC NC Clock pulse input NC NC Clock pulse input NC Power supply (Clamp) NC Signal output (G) Description
VOUT-EVEN (G) Signal output (G) VOUT-ODD (B) GND Signal output (B) GND
Recommended Supply Voltage Item VDD Min. 8.55 Typ. 9 Max. 9.45 Unit V
Clock Characteristics Item Input capacity of 1, 2 Input capacity of 2L Input capacity of RS Input capacity of ROG Input capacity of CLP Symbol C1, C2 C2L CRS CROG CCLP Min. -- -- -- -- -- Typ. 1800 60 60 60 60 Max. -- -- -- -- -- Unit pF pF pF pF pF
Note) Input capacity of 1, 2 is a value gathering respective related pins. -2-
ILX115LA
Clock Frequency Item 1, 2, 2L, RS CLP Symbol f1, f2, f2L, fRS fCLP Min. -- -- Typ. 1 1 Max. 15 10 Unit MHz MHz
Input Clock Pulse Voltage Item 1, 2, 2L, RS, ROG, CLP pulse voltage High level Low level Min. 4.75 -0.3 Typ. 5.0 0 Max. 5.25 0.1 Unit V V
Mode Description Pin condition 8pin CLP Clamp circuit not used Clamp circuit used VDD CLP 15pin SWCLP GND VDD
-3-
ILX115LA
Electrooptical Characteristics (Note 1) Ta = 25C, VDD = 9V, fRS = 1MHz, Input clock = 5Vp-p, Clamp circuit used, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm) Item Red Sensitivity Green Blue Sensitivity nonuniformity Saturation output voltage Red Saturation exposure Green Blue Dark voltage average Dark signal nonuniformity Image lag Supply current Total transfer efficiency Output impedance Offset level Symbol RR RG RB PRNU VSAT SER SEG SEB VDRK DSNU IL IVDD TTE ZO VOS Min. 5.10 5.17 5.48 -- 1.5 0.18 0.18 0.16 -- -- -- -- 92 -- -- Typ. 6.80 6.89 7.30 5 1.8 0.26 0.26 0.25 1.5 1.5 0.02 45 98 185 4.4 Max. 8.50 8.61 9.13 15 -- -- -- -- 3 5 -- 60 -- -- -- mV mV % mA % V Note 5 Note 6 -- -- -- Note 7 lx * s Note 4 % V Note 3 V/(lx * s) Note 2 Unit Remarks
Notes 1) In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D24, D26 to D72. The odd black level is defined as average value of D23, D25 to D71. 2) For the sensitivity test light is applied with a uniform intensity of illumination. 3) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. VOUT = 500mV (VMAX - VMIN) /2 PRNU = x 100 [%] VAVE Where the 5000 pixels are divided into blocks of 100, even and odd pixels, respectively the maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. 4) Saturation exposure is defined as follows. SE = VSAT/R [lx * s] 5) Optical signal accumulated time int stands at 10ms. 6) VOUT (B)= 500mV (typ.) 7) Vos is defined as indicated below. VOUT indicates VOUT-ODD (R), VOUT-EVEN (R), VOUT-ODD (G), VOUT-EVEN (G), VOUT-ODD (B), VOUT-EVEN (B).
VOUT

VOS GND
-4-
Clock Timing Chart 11
ROG
5
0
1
5
0
1
2
3
2 2L
5
0
RS
5
0
D1
D3
D5
D21
D23
D25
D61
D63
D65
S1
S3
S4995
S4997
S4999
D67
D69
D71
D73
D75
D77
D79
D81
D83
D85
D87 S5000 D68 D70 D72 D74 D76 D78 D80 D82 D84 D86 D88 Dummy signal (24 pixels)
VOUT-ODD (R) VOUT-ODD (G) VOUT-ODD (B) D2 D4 D6 D22 D24 D26 D62 D64 D66 S2 S4 S4996 S4998
VOUT-EVEN (R) VOUT-EVEN (G) VOUT-EVEN (B) Optical black (42 pixels)
Dummy signal (66 pixels)
Effective pixels (5000 pixels)
1-line output period (5090 pixels)
1 The transfer pulses (1, 2, 3) must have more than 2545 cycles.

D90
D89
-5-
CLP
5
0
2545
ILX115LA
ILX115LA
Clock Timing Chart 2
t4 t5
ROG t6
t2 t7
1
t1
t3
2 2L
Clock Timing Chart 3
t6 1 t7
2 2L t9 t10 t8
t15
RS t11 CLP t13 t16 VOUT t17 t18 t14 t12
,, ,
-6-
ILX115LA
Clock Timing Chart 4
Cross point 1 and 2 1 5V
2.0V (Min.) 2 0V
1.5V (Min.)
Cross point 1 and 2L 1 5V
2.0V (Min.) 2L 0V
0.5V (Min.)
Clock Pulse Recommended Timing Item ROG, 1 pulse timing ROG pulse high level period ROG, 1 pulse timing ROG pulse rise time ROG pulse fall time 1 pulse fall time /2 pulse rise time 1 pulse rise time /2 pulse fall time RS pulse rise time RS pulse fall time RS pulse low level period RS, CLP pulse timing 1 CLP pulse rise time CLP pulse fall time RS, CLP pulse timing 2 CLP 2L pulse timing Signal output delay time for RS Signal output delay time for CLP Signal output delay time for 2L Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 Min. 50 600 400 0 0 0 0 0 0 8 0 0 0 16 0 -- -- -- Typ. 100 1000 1000 10 10 5 5 5 5 2001 501 5 5 2001 701 12 4 12 Max. -- -- -- 100 100 10 10 10 10 -- -- 10 10 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1 These timing is the recommended condition under fRS = fCLP = 1MHz. -7-
Application Circuit1
VOUT-ODD (B) VOUT-ENEN (G) VOUT-ODD (G) 3.3F Buffer1 100 2 2 100 100 IC1
2L
1
1 ROG (G)
ROG (B)
Buffer1
44 1 NC NC NC NC NC NC NC NC 1 NC 2L VREF VDD VOUT-ODD (G) ROG (G)
43
Buffer1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25 ROG (B)
24 NC
23 NC
GND
VOUT-ODD (B)
VOUT-ODD (R)
VOUT-EVEN (B)
VDD
NC
RS
NC
CLP
NC
2
VOUT-EVEN (R) VOUT-EVEN (G)
NC
2
NC
ROG (R)
NC
NC
NC
NC
NC
9V 4 5 6 7 8 9 10 11 12 13 14
SWCLP
GND
NC
Buffer1
Buffer1
Buffer1
-8-
15 16 100 100 2 2 RS CLP 2 2
1
2
3
17
18
19
20
21
22
IC1: 74AC04
100
Buffer 1: IN 9V
0.1F 47F 16V
IC1
100 2SC2785 ROG (R) OUT 5.1k
VOUT-ENEN (R)
VOUT-ODD (R) VOUT-ENEN (B)
1 Data rate fRS = 1MHz.
ILX115LA
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
ILX115LA
Example of Representative Characteristics (VDD = 9V, Ta = 25C)
Spectral sensitivity characteristics (Standard characteristics)
1.0 0.8 0.6 0.4 0.2 0 400
Relative sensitivity
450
500
550 600 Wavelength [nm]
650
700
Dark output voltage rate vs. Ambient temperature (Standard characteristics)
100 10
Output voltage rate vs. Integration time (Standard characteristics)
Dark output voltage rate
10
Output voltage rate 0 10 20 60
1
1
0.1 -10
30
40
50
0.1
1
5 int - Integration time [ms]
10
Ta - Ambient temperature [C]
Offset level vs. Supply voltage (Standard characteristics)
10 10
Offset level vs. Ambient temperature (Standard characteristics)
8 Vos - Offset level [V] Vos - Offset level [V]
8
6
6
4
4
2
2
0
8.5
9.0 VDD - Supply voltage [V]
9.5
0 -10
0
10
20
30
40
50
60
Ta - Ambient temperature [C]
-9-
ILX115LA
Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer-DIP packages. a) Remain within the following limits when applying a static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm
Upper ceramic layer 39N 29N 29N 0.9Nm
, , , , , , ,
Lower ceramic layer (1) Low-melting glass (2) (3) (4)
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with a soldering iron. (3) Rapid cooling or heating. (4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered.
3) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. - 10 -
ILX115LA
4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
- 11 -
Package Outline
Unit: mm
A 89.0 1.0
44pin SDIP(400mil)
9
8.4 10.0 0.8 (AT STAND OFF) 10.16 3.90
~ 0.46 1. The point "A" of the package is the horizontal reference. The two points "A'" of the package are the vertical reference. 2. The height from the bottom to the sensor surface is 2.4 0.3m. 3. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5. 4. The notch of the package must not be used for reference of fixing.
2.0
~
V
5.0 0.5
H No.1 pixel(Blue) 84.0 A' 25.0 5.0 29.0 5.0 A'
6.68
4.0 0.5
- 12 -
~ 44.450
1.778
PACKAGE STRUCTURE
PACKAGE MATERIAL
Cer-DIP
LEAD TREATMENT
TIN PLATING
LEAD MATERIAL
42ALLOY
PACKAGE MASS
11.5g
ILX115LA
DRAWING NUMBER
LS-B15-01(E)
4.60 0.5
0.25
0 to
11.1 0.8 70.0(14mX5000Pixels)

▲Up To Search▲

Price & Availability of ILX115LA

	To Download ILX115LA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .